1. Field of the Invention
This invention relates to data processing systems and, more particularly, to an apparatus for queuing data between a central processor and a peripheral device.
2. Description of the Relevant Art
Data processing systems typically require storage devices in which data are temporarily stored during data transfers. Such devices are used to compensate for differences in processing rate of or event timing between two or more devices. One example of such a device is a first-in/first-out ("FIFO") buffer wherein data is stored sequentially at one rate and subsequently retrieved at another rate in the same order in which it was stored. FIFO buffers typically comprise a plurality of storage registers wherein data is shifted sequentially from an entry location to an exit location, the data being shifted one register position for each clock pulse.
One drawback with conventional devices is that the data must be shifted entirely through the shift register stages before it is available as output. This limits the speed at which the data may be transferred. Furthermore, conventional devices utilize edge triggered devices for each data bit in each shift register stage. This requires a substantial amount of hardware and poses substantial design problems when the circuit designer is allocated very little hardware space.